1. Field of the Invention
The present invention relates generally to methods and apparatus for bumping a wafer. In particular, the present invention relates to methods and apparatus of bumping a wafer and stitch wire bonding to the bumps as well as resulting assemblies and systems.
2. State of the Art
Chip-On-Board (“COB”) or Board-On-Chip (“BOC”) technology is well known and utilized for mechanically attaching and electrically connecting semiconductor dice directly to a carrier substrate such as a printed circuit board (“PCB”). Electrical connection in COB and BOC assemblies may be effected using various techniques such as wire bonding, tape automated bonding, and flip-chip attachment. Similarly, semiconductor dice may be attached and electrically connected to a carrier substrate in the form of a lead frame, such as a conventional die paddle lead frame and a leads-over-chip (LOC) lead frame.
Wire bonding is generally preceded by attachment of a semiconductor die to a carrier substrate with an appropriate adhesive, such as an epoxy, silver solder or adhesive-coated film or tape segment. A plurality of fine wires is then attached individually to each bond pad on the semiconductor die and extended and bonded to a corresponding terminal pad (or lead) of the carrier substrate. The assembly or at least a portion of the semiconductor die then may be encapsulated with a filled polymer by transfer molding, injection molding, pot molding, or with a mass of silicone or an epoxy in a so-called “glob top” encapsulation process.
There are several predominant types of wire bonding techniques, including aluminum wedge ultrasonic bonding and gold thermosonic or thermocompression stitch bonding. Although the gold thermosonic or thermocompression stitch bonding technique has an associated higher cost in materials than the aluminum wedge bonding technique, the gold thermosonic bond is faster to form. For example, gold thermosonic bonders are capable of production speeds of ten wires/second compared to speeds of aluminum wedge bonders of five wires/second.
As the sizes and pitches (spacing) of semiconductor die bond pads have continued to decrease in concert with ongoing miniaturization of integrated circuits, reduction of bond pad sizes has precluded the use of wirebonder capillaries to form stitch or wedge bonds on the bond pads due to damaging contact of the capillary with the relatively fragile and nonresilient (typically a glass) passivation layer surrounding the bond pads on the active surface. While a tilted orientation of wirebonder capillary end surface to prevent passivation layer damage has been proposed in U.S. Pat. No. 5,437,405 to Asanavest, this is not an ideal solution and the approach is still limited by ever-decreasing bond pad size. Accordingly, it has been proposed to form a ball bump or stud bump of conductive material on a bond pad preliminary to actual wire bonding, and then to form a protruding stitch bond to the previously formed ball or stud bump at a safe elevation above the surface of the passivation layer. U.S. Pat. No. 5,328,079 to Mathew et al. discloses forming a conductive bump with a wirebonder capillary to a bond pad of a semiconductor die and then subsequently stitch bonding to the bump to protect the surrounding area of the passivation layer surface. However, individually forming conductive bumps on the bond pads on a wafer to facilitate subsequent wire bonding thereto has proven to be neither cost effective nor time efficient.
Gold has been favored as a metal for stud bumping bond pads to which gold wires are to be stitch bonded. Specifically, bumping semiconductor die bond pads with a stud bump, typically gold, is conventionally used to provide a preferred contact for gold thermosonic or thermocompression bonding, as a gold stud bump provides an excellent contact for the gold wire, being easily bondable and providing a robust connection. Further, a gold stud bump formed on a bond pad results in a conductive structure displaced above the relatively fragile passivation layer surface of the die or wafer surrounding and at a substantially higher elevation over the active surface than the bond pads and provides a bonding surface for contact by a wire bonding capillary without the risk of contacting and damaging the surrounding passivation layer surface.
Gold stud bumps are formed with a thermosonic or thermocompression capillary, wherein the wirebonder capillary forms and releases a gold ball on each separate bond pad, individually and consecutively, until each bond pad on a wafer receives a gold stud bump. Some wafers conventionally include as many as about 11,400 bond pads and the 300 mm wafers now being implemented by the semiconductor industry will greatly increase this number. The instruments and capillary utilized for forming the gold bumps have optimum stud bumping speeds of about eight to ten balls/second. Thus, it would take approximately one hour to gold stud bump 2½ to slightly over 3 wafers having 11,400 bond pads each, depending on bumping speed. Since a wirebonder may have a capital cost in excess of one hundred thousand dollars, and acceptable bumped wafer throughput thus requires a large number of wirebonders in addition to the process time involved, it will be appreciated that the current approach to wafer bumping is less than optimum.
Therefore, it would be advantageous to form bumps on a wafer to enable the advantages of gold thermosonic or thermocompression bonding, but with greater throughput. It would also be advantageous to produce bumps on a wafer to enable stitch bonding without the excessive material costs of gold stud bumps.